1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a circuit for reducing the power consumption in the stand-by mode for the operation of a memory integrated circuit chip.
2. Description of the related art
In an integrated circuit of the conventional static random access memory (SRAM), for example, negative logic signal CE1 and positive logic signal CE2 for selectively specifying a stand-by mode/operative mode of the chip are used as a chip enable signal. Signals CE1 and CE2 are supplied to a chip enable input circuit as is shown in FIG. 1. Signal CE1 is supplied to one input terminal of NOR gate 81 and signal CE2 is inverted by inverter 82 and then supplied to the other input terminal of NOR gate 81. The output of NOR gate 81 is used as internal chip enable signal CEin.
In a case where signal CE2 is set at a low level ("L") as shown in FIG. 2, signal CEin is kept at a low level even if signal CE1 becomes active (low level). As a result, the internal circuit of the chip is set into the stand-by mode and the power consumption is suppressed to a minimum.
In contrast, when signal CE2 becomes active (high level "H") while signal CE1 is kept at the active level, signal CEin becomes high level and the circuit in the chip becomes operative. Therefore, it becomes necessary to hold signal CE2 at a low level while signal CE1 is kept at the low level in order to suppress the power consumption in the stand-by mode of the chip. For this reason, the condition of signal CE2 will be limited.
In order to eliminate the above limitation, a method in which signal CE2 (chip select signal CS) is taken into the internal circuit in synchronism only with the fall of signal CE1 as shown in FIGS. 4A and 4B is proposed. If signal CE2 is at a low level when taken into the internal circuit, the internal circuit is set into the stand-by mode by the low level of signal CEin (FIG. 4A), and if signal CE2 is at a high level, the internal circuit is set into the operative mode by the high level of signal CEin (FIG. 4B). In this way, signal CE2 is limited only at the time of fall of signal CE1, and is free in other period of time indicated by a hatched portion. However, in the stand-by mode shown in FIG. 4A, it becomes necessary to set the internal circuit operative in order to receive signal CE2 at the time of fall of signal CE1. Thus, if the internal circuit is operated, the power consumption increases.
It is also effected to set the data output buffer into the stand-by mode by output enable signal OE in order to suppress the power consumption of the internal circuit in the stand-by mode. However, even when the power consumption in the output stage is suppressed, the power consumption of the whole circuit cannot be sufficiently suppressed since other circuit portions of the internal circuit are operated.
As described above, in a case where the stand-by mode/operative mode of the internal circuit of the chip is controlled by two kinds of chip enable signals, the power consumption will be increased by taking the chip enable signal in the stand-by mode even if it is so designed that one of the two chip enable signals may be set normally free and will be limited only when the other chip enable signal is set active.